This application is related to Korean Application No. 2000-9178, filed Feb. 24, 2000, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to auto precharge control signal generating circuits for semiconductor memory devices and auto precharge control methods.
Auto precharge burst write operations are performed in synchronous dynamic random access memory SDRAM devices. An auto precharge burst write operation is used to perform precharge automatically after a given time tRDL from the last data input, after writing data in an amount of the burst length given when inputting a write command. A SDRAM having auto precharge operation is disclosed in U.S. Pat. No. 5,748,560.
Generally, auto precharge operations delay a column bank address signal corresponding to the burst length by a fixed clock in response to tDRL, and generate an auto precharge control signal by combining the delayed signal and the column bank address signal. In case that tRDL is equal to 2 clock cycles, an auto precharge control signal has to be generated after 1 clock cycle from End of Burst (EOB) has passed. Therefore, a column bank address signal indicating an EOB is typically delayed by 1 clock cycle and is used in generating an auto precharge control signal.
In an auto precharge operation, an auto precharge is determined according to when a next column command after an initial column command is applied. For example, if a command is applied in the form of an interrupt, a column bank address signal is not disabled and thus the auto precharge information applied in an initial time is lost and the precharge operation is not generated. In case that a command is applied in the form of 1 clock gap, in a condition that tRDL is 2 clock cycles, because the last data is not written into a cell, the precharge time point is the same time point as a command applied later. Thus, in this case, it is desirable that the precharge operation is performed in the different manner from the above-mentioned manner.
In case that a gap between a column bank address signal and a 1 clock cycle delay signal is 1 clock cycle and a burst write command is applied to the 1 clock gap, a margin is assured by delaying so that the trailing edge of 1 clock delay signal is located behind a leading edge of the next column bank address signal. But, in case that the length of a burst is 1, a column bank address signal becomes active in applying a command and becomes inactive at the next clock. Therefore, in case a phenomenon that the trailing edge of the column bank address signal and the leading edge of the 1 clock delay signal do not overlap, an unwanted precharge control signal may be generated.
An object of the present invention is to provide auto precharge control signal generating circuits of a semiconductor memory device and an auto precharge control method which prevents the generation of unnecessary auto precharge control signals due to the crossing of a 1 clock delay signal and a column bank address signal in the middle of continuous burst write operation. This is achieved by setting the timing of the delay signal so that an active period of the 1 clock delay signal includes a sufficient gap between column bank address signals, when the burst length is 1 and the time from the last data input to an auto precharge is 2 clock cycles (in case that a burst write command is applied at intervals of 1 clock).
According to one aspect of the present invention, to accomplish the object, a circuit of a preferred embodiment includes output enable means which is reset in response to a precharge operation and generates an output enable signal by latching an auto precharge command signal in an active period of a column bank address signal. Delay means also is provided. The delay means generates a 1 clock delay signal by delaying the active period of the column bank address signal by 1 clock, and generates a 1 clock delay signal having an active period that sufficiently covers a non-active period between a previous column bank address signal and a present column bank address signal in the event the burst length is 1. Assembly means also is provided. The assembly means generates an auto precharge control signal by combining the column bank address signal and the 1 clock delay signal in response to the output enable signal. This auto precharge control signal controls auto precharge after delaying it 2 clock cycles from the input time point of the last data, in response to a continuous auto precharge burst write command.
The delay means includes input latch means, which is set by the column bank address signal and is reset by the output enable signal, and latch means which inputs an output signal of the input latch means at a falling edge of a clock signal and outputs at a rising edge of the clock signal. An auto pulse generation means also is provided which delays an output signal of the latch means so that a back part of a 1 clock delay signal (responding to a previous auto precharge burst write command) is located next to a front part of a column bank address signal (responding to a present auto precharge burst write command). The auto pulse generation means also generates the 1 clock delay signal by extending an active period of an output signal of the latch means so that the front part of a 1 clock delay signal is located before the back part of a column bank address signal, in case the burst length is 1.
The auto pulse generation means also may include a delayer that delays an output signal of the clock synchronous latch means for a fixed time, a switching means that switches an output signal of the latch means in response to a burst length 1, and a NAND gate that generates a 1 clock delay signal by combining an output signal of the delayer and an output signal of the switching means.
Also, an output enable means includes a switching means for switching an auto precharge command signal at a falling edge of a clock signal in an active period of the column address signal in response to the precharge operation. The output enable means also includes an inversion latch means that generates an output enable signal by latching an output signal of the switching means. Reset means also is provided for resetting the inversion latch means in response to the precharge operation. A combining means includes a NOR gate that receives the 1 clock delay signal and the column bank address signal, and a NAND gate that receives the output of the NOR gate and also receives the output enable signal.
An auto precharge control method can be performed during an auto precharge burst write operation. This method comprises the steps of generating a column bank address signal having an active period corresponding to burst length (during auto precharge burst write command), in response to a rising edge of a clock signal. The column bank address signal also is latched at a falling edge of a clock signal. The output enable signal also is generated by latching an auto precharge command signal at a falling edge of the clock signal, after input-latching the column bank address signal. The input-latched column bank address signal also is output latched at a rising edge of the next clock signal. The 1 clock delay signal also is generated by delaying the output-latched column bank address signal or generating a 1 clock delay signal having an active period including a non-active period sufficiently between the previous column bank address signal and the present column bank address signal in case the burst length is 1. These steps are repeated if there is a next continued auto precharge burst write command. Otherwise, an auto precharge control signal is generated which becomes active at an end part of the 1 clock delay signal and becomes non-active by the output enable signal.
The present invention can prevent the generation of an unwanted auto precharge control signal and makes it easy to design a delay circuit. The auto precharge control signal is generated by combining a column bank address signal having EOB information and a signal obtained by delaying the signal by 1 clock.